1. Field of the Invention
The present invention relates to a focus area change circuit. More specifically, it relates to a focus area change circuit which changes a focus area designated for controlling the focus of a video camera.
2. Description of the Prior Art
Video signals obtained through a video camera are maximized in amount of change in an in-focus state. Therefore, proposed is a method of controlling the focus of a video camera by sampling video signals to detect luminance level change and levels of high-frequency components of luminance signals.
FIG. 1 illustrates a display mode of a conventional focus control position display circuit and FIG. 2 illustrates arrangement of pushbutton switches of the conventional focus control position display circuit, while FIG. 3 is a block diagram showing the conventional focus control position display circuit.
With reference to FIGS. 1 to 3, description is now made on the structure and operation of the conventional focus control position display circuit. The focus control position display circuit as shown in FIGS. 1 to 3 is adapted to switch a focus control position at desire by manipulating four pushbutton switches B1, B2, B3 and B4 respectively corresponding to vertical and horizontal directions of movement. In the example as shown in FIGS. 1 to 3, a video camera for recording still pictures has a focus control function to set the focus control position in advance to recording and the focus control position is displayed on an electronic view finder associated with the same, and sample prescribed video signals immediately before starting recording to move the focus lens to maximize change in the luminance level. Thereafter the video signals for one field are recorded on a prescribed track.
More concretely, luminance signals are supplied to a delay circuit 1 and one input end of a differential amplifier 2. The delay circuit 1 is adapted to delay the luminance signals by 1/800f.sub.H, to supply the delayed luminance signals to the other input end of the differential amplifier 2, which in turn supplies differential signals to an absolute value circuit 3. The absolute value circuit 3 performs full-wave rectification of the differential signals and the outputs thereof are converted into four-bit data of signals of 800f.sub.H. A RAM 5 stores the data for 100 samples.
The added value of the data stored in the RAM 5 is a barometer of the level change of the luminance signals, and a microcomputer (not shown) controls a focus control motor (not shown) to maximize the added value.
The aforementioned pushbutton switches B1 to B4 are pressed to close first to fourth switches S1 to S4 thereby to enable preset of sampling positions. Namely, the first switch S1 is closed to supply a shift clock pulse of 100 Hz to a first presetable counter 6, thereby to count up the same. The second switch S2 brings the first presetable counter 6 in a downcount mode while supplying a shift clock pulse to the first presetable counter 6 thereby to count down the same.
In a similar manner, the third switch S3 brings a second presetable counter 7 in an upcount mode while the fourth switch S4 counts down the second presetable counter 7. The preset value of the first presetable counter 6 defines the focus control position in the horizontal direction and the preset value of the second presetable counter 7 defines the focus control position in the vertical direction.
The preset value of the first presetable counter 6 is compared with the count value of a first counter 9 by a first comparator 8. The first counter 9 receives horizontal synchronizing signals of video signals as reset inputs while receiving signals 512 times the said horizontal synchronizing signals in frequency as count inputs. Thus, the first comparator 8 generates a first detection output when the preset value of the first presetable counter 6 coincides with the count value of the first counter 9.
The preset value of the second presetable counter 7 is compared with the count value of a second counter 11 by a second comparator 10. The second counter 11 receives vertical synchronizing signals as reset inputs while receiving the horizontal synchronizing signals as count inputs. Thus, the second comparator 10 generates a second detection output when the said preset value coincides with the count value of the second counter 11.
The first detection output generated from the first comparator 8 is supplied to a 1/64 frequency divider 12, a 1/31 frequency divider 13 and first and second flip-flops 14 and 15. The 1/64 frequency divider 12 and 1/31 frequency divider 13 are reset by the first detection output, while the first and second flip-flops 14 and 15 are set by the same. The 1/64 frequency divider 12 receives a signal of 512 f.sub.H as a count input, to supply an output signal to the first flip-flop 14 at the timing escaping a sampling range of about 1/8 in the horizontal direction, thereby to reset the first flip-flop 14. Thus, the first flip-flop 14 is turned to a high level in a sampling range of 100 data in the horizontal synchronizing interval. The 1/31 frequency divider 13 generates an output at the timing immediately ahead of the central point of the sampling range, thereby to reset the second flip-flop 15. At the fall timing of the second flip-flop 15, a first monostable multivibrator 16 is triggered to derive a high-level signal of certain width at the center of the sampling range.
In a similar manner, the second detection output from the second comparator 10 is supplied to a 1/5 frequency divider 17 and a 1/2 frequency divider 18 respectively as the reset input, as well as to third and fourth flip-flops 19 and 20 as the set input. The 1/5 frequency divider 17 is adapted to divide the horizontal synchronizing signal, thereby to reset the third flip-flop 19 by its division output. Thus, the third flip-flop 19 is turned to a high level by a period of 5H upon generation of the second detection output. In a similar manner, the 1/2 frequency divider 18 divides the horizontal synchronizing signal, to reset the fourth flip-flop 20 by its outputs. A second monostable multivibrator 21 is triggered at the fall timing upon reset of the fourth flip-flop 20, and the monostable period thereof is about 1H. Thus, the output of the second monostable multivibrator 21 is turned to a high level for a 1H period after a lapse of 2H from generation of the second detection output.
An AND gate G5 obtains the logical product of the respective outputs of the first monostable multivibrator 16 and the third flip-flop 19, to supply the same as a switching control input to a switching circuit 22. On the basis of the switching control input, the switching circuit 22 switches the video signals and white level output signals. The switching circuit 22 displays a white bar on the focus control position on the monitor screen.
The respective outputs from the first flip-flop 14 and the second monostable multivibrator 21 are supplied to an AND gate G6, which in turn obtains the logical product output which is turned to a high level in a sampling range of once per field. The output of the AND gate G6 is supplied to one input end of an AND gate G7, which obtains the logical product of the same and an 800 f.sub.H sampling signal received in the other input end, to supply its output to an address counter 23. The address counter 23 stores 100 data per A-D conversion by the A-D converter 4 while designating addresses of the RAM 5 by its count outputs.
In the conventional focus control position display circuit of the above structure, the pushbutton switch B1, B2, B3 or B4 is manipulated to close the contact of the switch S1, S2, S3 or S4 to select a desired area on the screen for controlling the focus, while displaying the selected area on the electronic view finder.
However, although the focus control area can be vertically or horizontally changed by manipulating the pushbutton switches B1 to B4, the range thereof cannot be expanded and hence the focus cannot be completely controlled in the aforementioned focus control position display circuit.